1. Field of the Invention
The present invention concerns integrated circuits (ICs) and IC design, and particularly relates to the utilization of off-grid metal layer resources on an integrated circuit.
2. Description of the Related Art
FIG. 1 provides a simplified cross-sectional view of an integrated circuit chip (or die) 10, which includes a semiconductor layer 5, three metal layers 1 to 3, electrically insulating layers 7, and passivation layer 8. Semiconductor layer 5, which is typically polysilicon, is used for forming the transistors and other electronic devices and also may be used for routing some of the electrical connections between these electronic devices. However, wire routing occupies space on the semiconductor layer 5 which otherwise could be used for the electronic devices. As a result, ordinarily only the shorter electrical connections are formed on semiconductor layer 5. For the remainder of the connections, metal layers 1 to 3 are provided.
Metal layers 1 to 3 may be formed from any of a variety of materials including aluminum, copper or an electrically conductive alloy. Typically, two to four metal layers are formed on top of semiconductor layer 5. To simplify the routing process, routing typically is performed using mainly horizontal and vertical trace (or wire) segments. Moreover, to permit such routing to be performed in an orderly manner, each metal layer typically is designated as either a horizontal metal layer or a vertical metal layer. Horizontal metal layers are used primarily for horizontal wire segments and vertical metal layers are used primarily for vertical wire segments. By routing wires in the metal layers 1 to 3, electrical connections can be made without using valuable space on semiconductor layer 5. Between metal layers 1 and 2, between metal layers 2 and 3, and between metal layer 1 and semiconductor layer 5 is an electrically insulating layer 7, which typically is formed as an oxide film. Connections between metal layers or between the metal layers and connections between a metal layer, other than metal layer 1, and semiconductor layer 5 are made using interlayer holes called vias. Direct contacts are made between semiconductor layer 5 and metal layer 1.
Passivation layer 8 functions to prevent the deterioration of the electrical properties of the die caused by water, ions and other external contaminants. Typically, passivation layer 8 is made of a scratch-resistant material such as silicon nitride and/or silicon dioxide.
FIG. 2 provides a representational illustration of the layout of the logic portion 20 of integrated circuit die 10. Logic portion 20 generally is located at the interior of die 10. Typically, along the periphery of the IC die are I/O buffer cells (not shown) for interfacing with devices external to die 10. As shown in FIG. 2, logic portion 20 is bordered by a power (VDD) ring 21 and a ground (VSS) ring 22. Vertical power rails 24 bring power and vertical ground rails 25 bring ground to the internal logic electronic components from the power ring 21 and ground ring 22, respectively. Specifically, as shown in FIG. 2, various logic cells 27 are arranged in cell columns 28, with each cell column 28 being bordered by a power rail 24 and a ground rail 25. Although FIG. 2 shows a significant gap between cell columns 28, the actual gap may in fact be much smaller. Overlaying cell columns 28 are channels 29. For example, each channel 29 may be defined as the space from the left side of one cell column 28 to the left side of the next cell column 28.
Each cell 27 includes one or more predetermined gates, flip-flops and/or other basic electronic devices. Also as shown in FIG. 2, each cell 27 typically has a standard width, although its length may be different from that of other cells. Although interior portion 20 is referred to herein as the logic portion of the IC and cells 27 are referred to herein as logic cells, this terminology is used merely to distinguish those cells from the I/O buffer cells. It should be understood that certain cells 27 may include some or all non-logic processing, such as analog signal processing.
Power and ground rings 21 and 22 and power and ground rails 24 and 25 usually are formed on the die""s metal layers. In certain implementations, vertical wire segments are formed on metal layers 1 and 3 and horizontal wire segments are formed on metal layer 2 in addition to supplying power and ground, metal layers 1 to 3 also are used for routing electrical connections for carrying signals between and within the cells 27.
In the layout described above, in which cell columns are used, the routing problem typically is separated into intra-column and inter-column routing. In intra-column routing, electrical connections are routed between electronic components in the same cell column, while in inter-column routing electrical connections are routed between cells in different cell columns. The routing problem is divided in this manner because the considerations involved in intra-column routing are usually different than the considerations involved in inter-column. Most of these considerations arise from the fact that a greater proportion of intra-column routing is performed over cells, as compared with inter-column routing. In addition because direct contacts can be formed between semiconductor layer 5 and metal layer 1, there is no need to use vias, which typically occupy additional space, when routing over cells on metal layer 1. Because most of intra-column routing is over cells, it is often preferable to perform as much intra-column routing on metal layer 1 as possible. Moreover, routing over cells often imposes additional wire spacing requirements, such as limitations on routing over noise-sensitive circuitry.
Thus, in one conventional technique metal layer 1 initially is used for intra-column routing. This technique is illustrated in FIG. 3A, which depicts intra-column routing on metal layer 1 for a single cell column 40. Because point-to-point routing is performed entirely on metal layer 1, horizontal trace segments, as well as vertical trace segments, are implemented on metal layer 1, even though metal layer 1 is designated as a vertical metal layer. Moreover, metal layer 1 intra-column routing is performed independently of the grid used for cell placement and inter-column routing (as described below). In this regard, due to the absence of vias, the relatively fewer pins to connect and relatively smaller area in which to connect them, and the desire to perform as much intra-column routing as possible on metal layer 1, the inefficiencies of grid-based routing generally are thought to outweigh its advantages for this purpose. For reference purposes, vertical grid lines 42 used for placement and inter-column routing (discussed below) are shown in FIG. 3A. Corresponding horizontal grid lines also exist but are omitted from FIG. 3A for the sake of clarity.
In FIG. 3A, electrical connections are routed between the pins of cells 45, 46 and 47, as well as internally within those cells. As shown in FIG. 3A, routing is performed in a manner which tends to make the most efficient use of metal layer 1, independent of the grid lines. Thus, for example, pin 50 of cell 46 is connected to pin 52 of cell 47 using a wire trace which consists of vertical wire segment 54A, horizontal wire segment 54B and vertical wire segment 54C. As indicated above, each of segments 54A, 54B and 54C is implemented on metal layer 1.
FIG. 3B illustrates inter-column routing in this technique. As shown in FIG. 3B, inter-column routing is generally grid-based, meaning that the axial line of each wire segment generally is required to lie along a grid line in a predetermined, regularly spaced rectangular grid. Use of such grid-based routing often greatly simplifies the routing problem. Thus, as shown in FIG. 3B, the axial line of each inter-column wire segment is coincident with one of the vertical grid lines 42 or the horizontal grid lines 43. In this particular implementation, metal layers 1 and 3 are vertical metal layers and metal layer 2 is a horizontal metal layer. Accordingly, the horizontal inter-column wire segments 41 are implemented using on-grid resources on metal layer 2. Similarly, the vertical inter-column wire segments. 41 are implemented using on-grid resources on metal layers 1 and 3. However, inter-column routing is performed after metal layer 1 intra-column routing, and ordinarily there will be little if any on-grid over-the-cell resources on metal layer 1 after completion of metal layer 1 intra-column routing. As a result, mainly the channel portions of metal layer 1 are used in inter-column routing.
One example of inter-column routing shown in FIG. 3B is trace 67 between pin 64 of cell 61 and pin 65 of cell 62. Trace 67 consists of horizontal wire segment 67A, vertical wire segment 67B and horizontal wire segment 67C. Segments 67A and 67G are implemented on metal layer 2, while segment 67B is implemented on either metal layer 1 or metal layer 3.
In addition to performing inter-column routing, this step also performs intra-column routing, in a similar manner to the inter-column routing, for any intra-column connections not capable of being completed in the metal layer 1 intra-column routing step described above. That is, any such pins are connected by using on-grid channel-routing. For instance, a connection is routed between pin 74 of cell 71 and pin 75 of cell 72, both in cell column 70, by routing a horizontal wire segment 76A from pin 74 into adjacent channel 80, routing a vertical wire segment 76B in channel 80, and then routing another horizontal wire segment 76C to pin 75. Segments 76A and 76C are routed on horizontal metal layer 2 and segment 76C is routed on either vertical metal layer 1 or vertical metal layer 3. Vias connect segment 76A to pin 74, segment 76B to segment 76A, segment 76C to segment 76B, and pin 75 to segment 76C.
The foregoing routing technique of performing intra-column routing on metal layer 1 independently of the grid and then grid-based routing for all remaining connections provides good metal utilization for both over-the-cell and channel routing in many cases. However, an even more efficient metal utilization technique is desired. Specifically, the conventional techniques sometimes result in a situation in which a particular cell layout can not be routed. In these situations, adjustments to cell layout generally must be made and then routing retried, thus lengthening the design process. In other cases when using such conventional techniques, the die size must be increased to provide sufficient space for wire routing, thereby increasing the cost of the resulting integrated circuit.
The present invention addresses the foregoing problems by routing an electrical connection between cells in different cell columns by identifying and using an available off-grid resource within a cell column.
Thus, in one aspect the invention is directed to routing of electrical connections between cells arranged in cell columns on an integrated circuit (IC) die. Electrical connections are routed on a routing layer between cells located in a first cell column. An identification is made of an available off-grid resource capable of being used for wire routing that is both within the first cell column and on the routing layer. An electrical connection is routed between a first cell and a second cell located in different cell columns using at least a portion of the identified available off-grid resource.
In another aspect, the invention is directed to routing electrical connections between cells arranged in cell columns on an integrated circuit (IC) die. Electrical connections are routed on a routing layer between cells located in a first cell column. An identification is made of an available off-grid resource capable of being used for wire routing that is both within the first cell column and on the routing layer. An electrical connection is routed between a first cell and a second cell located in different cell columns, using grid-based routing in a channel between the first cell and the second cell and using at least a portion of the identified available off-grid resource.
By virtue of the foregoing arrangements, additional resources often can be used for routing. As a result, the invention may provide a technique for routing layout designs which are not capable of being routed using certain conventional techniques. Moreover, by increasing the likelihood of obtaining a routing solution, the present invention can avoid the necessity of re-designing the layout in certain cases, thereby reducing design time and cost.
In more particularized aspects of the invention, the identified off-grid resource is used to move a pseudo-pin generated in global routing. By utilizing the identified off-grid resource in this manner, the present invention can provide additional routing resources frequently without significant changes to the existing routing process.
The present invention also addresses the prior art problems discussed above by providing an integrated circuit die which includes an electrical connection having an on-grid wire segment in a channel and an off-grid wire segment formed in a cell column.
Thus, according to a still further aspect, the invention is directed to an integrated circuit die which includes vertical power rails and vertical ground rails. Cell columns, including a first cell column and a second cell column, are each bordered by a vertical power rail and a vertical ground rail. A channel is provided between the first cell column and the second cell column. An electrical connection is provided between a first electronic component in the first cell column and a second electronic component in the second cell column. The electrical connection includes an on-grid wire segment in the channel between the first cell column and the second cell column and an off-grid wire segment formed in one of the cell columns.
By utilizing on-grid and off-grid resources in the foregoing manner, an integrated circuit according to the present invention frequently can be both relatively easy and efficient to route.
The foregoing summary is intended merely to provide a brief description of the general nature of the invention. A more complete understanding of the invention can be obtained by referring to the claims and the following detailed description of the preferred embodiments in connection with the accompanying figures.